1. Technical Field
The present invention relates to digital circuit control, and particularly to a voltage stabilizer and a method for controlling a digital circuit unit.
2. Background Information
To ensure reliable operation of devices that contain digital circuits, fluctuations in the supply voltage must be taken into account in the design of digital circuit units. These fluctuations are partially caused by the voltage generator, and are partially attributable to the voltage drop in the wiring for the on-chip power supply.
The fluctuations of the voltage generators have static and dynamic portions. The static portion can be 10-20 mV, for example, and is attributable to tolerances of the components in the control loop for the voltage. The dynamic portion in the fluctuations is primarily attributable to load change. In conventional circuits, load changes with factors of up to 10 are quite usual, attributable, for example, to the switching over between different operating modes. For example, these load changes can result from a change of operating mode between low processing capacity and an operating mode with high processing capacity. The arising load change can occur from one clock to the next, which means within a few nanoseconds.
FIG. 1 shows a digital circuit unit on a circuit board or on a chip according to prior art. This has a voltage source 11 and a capacitor 12 Cout at the output of the voltage source or voltage generator. The resistances of the lines are symbolized by the two resistors 13. The voltage source 11 feeds a circuit block 15 arranged on a circuit board or a chip 14, bond or bump inductances 16 arising at the connection area of the circuit on the chip. To optimize the power supply, blocking capacitors 17 are provided, which serve to buffer charge for load changes. If the circuit block 15 is now to be activated as shown in FIG. 2, or if a load change occurs from a variation of the operating mode, conditioned for example by the activation of various circuit blocks, then a load change of 300 mA can arise within 10 ns, for example. In mobile telephones, for example, there can be load changes from 50 mA for speech processing to 350 mA for multimedia processing. The upper graph in FIG. 2 shows the current flow for the load change, the intervals not being drawn true to scale. The high or the lower activity can last about 1/10 sec., for example, while the transition between the different activities lasts 10 ns. The blocking capacitors 17 provided in FIG. 1 are too slow to be able to balance out such transient load changes, so that voltage fluctuations 21 and 22 arise in the supply voltage. These dynamic voltage fluctuations can be +/−50 mV, so that the supply voltage VDDnorm can fluctuate between VDDmax and VDDmin.
The dynamic or transient fluctuations of the voltage generators can be +/−50 mV, for example. This fluctuation amplitude means that in a variance at low values the switching speed is reduced by up to 10%, or that a maximum voltage lower by 50 mV must be used to exceed the maximum permissible voltage when a dynamic variance occurs at higher voltage values. A consequence of the latter is that the maximum possible switching speed becomes 10% lower.
The use of blocking capacitors to avoid these fluctuations in the supply voltage is known. This blocking capacitor is charged to the relevant supply voltage. If necessary, current or charge can then be released, when a sudden charge requirement occurs on a load change. Such blocking capacitors are additional components and must also have suitable dynamic properties as well as the necessary capacitance. Off-chip capacitors have the necessary capacitance, but do not prevent the voltage fluctuations caused by bond or bump inductances. Further known are on-chip capacitors, which are fast, but mostly only have a low capacitance and are expensive in their chip area requirement. Therefore a need exists to eliminate or reduce the dynamic fluctuations of the supply voltage.